Hardware design debugging is the process of finding or locating errors in designs after verification methodologies and techniques determine the presence of such errors. Design debugging is considered a major bottleneck in the overall hardware design cycle which consumes over 30% of the design effort. Today, design debugging is performed almost exclusively manually by hardware designers and verification engineers using graphical navigation tools. This is a tedious, time consuming and costly manual process.
A typical hardware design cycle starts with a specification document which describes the functionality, timing and general constraints of the design. The specification is used to both create the design, typically implemented in Hardware Description Language (HDL), and to determine the expected behaviour specified by the verification environment. HDL designs are most commonly implemented at the Register Transfer Level (RTL) using Verilog™ or VHDL. This approach to hardware design typically uses hierarchical and modular design concepts, where blocks or sub-designs are instantiated inside one another and connected together. Hierarchical and modular development is favoured as it is ideal for design reuse, development in a large group, and for verification and debugging among others.
A typical verification environment is composed of a web of advanced tools, methodologies and techniques. Each verification component has a set of strengths and weaknesses which make it ideal of specific verification tasks. Popular verification approaches include the use of one or more of the following:                Simulation engines driven by testbenches (hand written or automatically generated). Known as the work horse of verification, simulation engines are used extensively to quickly test a wide range of input stimuli and find errors quickly. In practice, simulation engines can rarely be used to prove the correctness of a design.        Formal verification tools. Used to formally verify specific properties, corner cases, or equivalences with other designs or models. Due to their slow performance compared to simulation engines, they are employed to prove conformity of important properties.        Semi-formal tools. These use a combination of simulation and formal techniques to verify properties, corner cases and increase verification coverage. They balance the strengths and weaknesses of both approaches.        
Each of the above approaches compares the design against a model derived from the specifications to determine whether the design demonstrates a correct or erroneous behaviour.
If the verification methodologies and techniques determine that an error exists in the design (i.e. verification fails), then the design is debugged to find the exact error source. Debugging is a manual task where the verification engineer typically uses the erroneous response of the design, the expected behaviour as stated by the specifications, and the input stimuli to determine what modules, gates, HDL statements or signals are responsible for the erroneous behaviour. The manual debugging process typically starts by examining the erroneous primary outputs and tracing all suspect gates, signals, and modules backwards through the design. Graphical navigation tools can be used to ease the manual tracing process. Suspect components are those whose values appear to be inconsistent with those of the specifications. Needless to say, debugging is usually an ad-hoc hoc process where the verification engineers' knowledge of the design and debugging experience play a major role in the efficiency of the process.
Once a suspect error source is found, the verification engineer attempts to correct the error and reruns the verification step to ensure that the problem has been rectified. In practice, finding the actual error source and correcting the problem is done in a trial-and-error manner where many iterations may be needed until the error is removed. FIG. 1 illustrates a verification and debugging process starting from a design specification.
One particular debugging approach was disclosed in U.S. Pat. No. 6,366,874 to Lee et al., which teaches a system and method for browsing graphically an electronic design based on a hardware description language specification. According to the technique, a user interacts with the system to browse or navigate through the design to find the error locations manually. However, the approach is not automated, requiring the constant input of a user. As well, the solution is tied to a particular graphical representation of the problem.
Other diagnosis methods have been proposed. For example, path tracing is a diagnosis technique that can be used find an error source in a gatelevel representation of a design given a set of input/output vectors that demonstrate the erroneous behaviour [1]. This technique traverses the gatelevel circuit backwards starting at the primary inputs and identifies a set of gates that may be responsible for the erroneous behaviour.
Symbolic simulation (or BDDs) can be used as a means to diagnose erroneous gatelevel designs [2]. The circuit and vectors are used to build a BDD which can be solved to find the gates responsible for the erroneous behavior.
Furthermore, SAT-based debugging solves the diagnosis problem by building a constrained satisfiability problem and uses a SAT solver to find solutions to the problem [3]. The inputs to the problem are a gatelevel circuit and a set of vectors used to detect the error. The output is a set of gates that may be responsible for the erroneous behaviour.
These are example of diagnosis methods and tools that work on the gate/logic level but do not extract capture information from the HDL level and do not translate the results back to HDL. These approaches are different from a hierarchical approach because they only work on the gatelevel (or logic level) and do not consider modular or hierarchical information. In addition, these known techniques do not implement a Quantified Boolean Formula (QBF) approach.
An automatic debugging approach was disclosed in U.S. patent application Ser. No. 11/556,466 to Veneris et al., which teaches a method, system and computer program for automated debugging for pre-fabricated digital synchronous hardware designs implemented in HDL. Required information is captured by interacting with the verification environment after verification fails. This capture information is used to build a diagnosis problem where the solution is a set of logic level error sources. Using the HDL information, the error at the logic level is translated to gates, modules, statements, and signals in the HDL description. The diagnosis problem can be solved efficiently formulating a Quantified Boolean Formula (QBF) problem and also by using the hierarchical and modular nature of the HDL design during diagnosis.
The Veneris application introduces various techniques for debugging. The present invention presents new techniques for debugging. Although most of these techniques are developed for automated debuggers, some may be used for manual debugging also.
In the drawings, one embodiment of the invention is illustrated by way of example. It is to be expressly understood that the description and drawings are only for the purpose of illustration